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I. Process Precision: Dual breakthroughs of advanced and mature technologies
Process precision is the core indicator of process capability, with transistor gate line width, structural innovation, and integration density as the core measurement standards: 
Advanced process leading: We have achieved 3nm FinFET process mass production, with logic area transistor density reaching 202 MTr/mm². Using FinFlex fin configuration technology, it can flexibly switch between 3-2 fin high-performance mode and 2-1 fin energy efficiency mode, increasing the driving current by 18% while reducing leakage rate by 34%. 2nm GAA (ring gate) process has entered the ramp-up period of mass production. The nanowire thickness is only 3nm, the gate length is reduced to 6nm, transistor density exceeds 313 MTr/mm², SRAM storage density reaches 38 Mb/mm², and compared to the 3nm process, energy efficiency increases by 30%. 
Stable mature process: 28nm-180nm processes form a standardized production capacity matrix. Relying on DUV lithography technology, stable production is achieved. Optimizing BCD (bipolar-CMOS-DMOS) mixed processes for automotive electronics and IoT scenarios, the yield is generally maintained above 95%, with 40nm MCU process monthly production exceeding 150,000 pieces, supporting automotive-grade AEC-Q100 certification. 
Lithography and etching precision: Advanced processes adopt EUV extreme ultraviolet lithography technology to precisely define 6nm gate lengths; the etching process supports 3D structure etching, with critical dimension (CD) control accuracy reaching ¡À1nm, process capability index (CPK) stable at over 1.33, ensuring that 99.99% of products fall within the specification range. 
II. Capacity Scale: Efficient supply system for full-size wafers
Capacity scale reflects the implementation capability of the process, with quantitative support through wafer size, monthly production capacity, and capacity utilization rate: 
Wafer size coverage: Establishing full-size production capacity for 8-inch (200mm) and 12-inch (300mm). The proportion of 12-inch wafer production lines exceeds 60%, the number of chips per wafer that can be arranged has increased by 40% compared to 8-inch, the incomplete Die ratio has dropped to 10.8%, significantly increasing effective output; the 8-inch production line focuses on mature processes, with monthly production exceeding 650,000 pieces, mainly supplying power devices, PMIC, and other automotive and industrial chips. 
Capacity gradient layout: 10,000 pieces per month of 3nm advanced process, 40,000 pieces per month of 2nm process by the end of 2025; the combined monthly production capacity of mature processes from 28nm to 90nm exceeds 800,000 pieces, with a dedicated capacity for automotive-grade chips accounting for 35% of the total, and capacity utilization rate stable at over 90%. 
Production cycle control: The time from pilot production to achieving production yield standards for advanced processes is shortened to 12 months, with 85% rapid breakthrough in 3nm process production yield; mature processes achieve rapid delivery within 45 days, supporting flexible production of multi-variety small-batch orders. 
III. Quality Control: Precise control system throughout the process
With yield improvement and defect control as the core, establish a quality assurance capability covering the entire process chain: 
Yield control capability: Through multi-dimensional monitoring such as wafer defect detection (ADI/AEI) and electrical tests (CP/FT), the yield of advanced process 12-inch is over 85%, and the yield of mature processes exceeds 95%. Using chip binning technology, performance-deviant chips are classified into different grades for utilization, for example, unstable chips at 2GHz target frequency but stable at 1.5GHz are classified for reuse, resulting in an overall yield improvement of 8-12 percentage points.
Process stability: The CPK (Process Capability Index) of key process parameters has consistently remained above 1.33. The ¦Ò value for CD uniformity in the lithography process is controlled within 0.3nm, and the etching depth deviation is less than 2%. A "continuous three deviations from the target" alarm mechanism has been established to adjust process parameters in real time and prevent the occurrence of systematic defects. 
Reliability certification: Passed strict certifications such as AEC-Q100 (automotive grade) and ISO 26262 (functional safety). The pass rates of reliability tests such as high-temperature storage (150¡æ/1000h) and temperature cycling (-55¡æ~125¡æ/1000 times) are 100%, and the FIT (failures per 1000 hours) is lower than 0.1-fit.


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